In recent years, the development of SiP (System in Package) which realizes a high performance system in a short period by packaging a plurality of semiconductor chips (simply referred to as “chip”) in high density has been promoted, and various packaging structures have been proposed. More particularly, the development of a stacked-type package which can realize a significant downsizing by stacking a plurality of chips has been promoted actively. Normally, the wire boding is used for the electrical connection between chips. This is because the wire bonding has high degree of freedom in layout and is effective for the connection of the plurality of semiconductor chips.
However, in the wire bonding connection, since it is required that a wire led out from one chip is once connected to a mounting board and the wire is then re-connected to another chip, a wire length between chips becomes long. Consequently, an inductance between chips is increased, and the high-speed transmission becomes difficult. For the issues in the wire bonding connection, a Si (silicon) through-hole electrode technique in which an electrode penetrating through the chip is formed to directly connect the chips has been suggested.
Japanese Patent Application Laid-Open Publication No. 2000-260934 (Patent Document 1) discloses such a technique that electrodes obtained by burying solder or low melting point metal into the through-hole portions formed inside the chips by the electrolytic or electroless plating method are provided on upper and lower portions of the chips, and the chips are stacked and then heated, so that the chips are three-dimensionally stacked by the fusion bonding of the buried electrodes.
Also, Japanese Patent Application Laid-Open Publication No. 2007-053149 (Patent Document 2) discloses such a technique that a stud bump formed in an upper chip is deformed and injected into a hollow through-hole electrode formed in a lower chip by pressure welding, and the stud bump and the through-hole electrode are geometrically caulked, so that the chips are stacked.